1. Field of the Invention
The invention relates to a signal sampling apparatus, and more particularly, to a signal sampling apparatus having a sample and hold circuit.
2. Description of the Prior Art
Sample and hold circuits have been utilized in many circuits. For example, a sample and hold circuit can be utilized in an analog to digital converter, placed inside an optical disk drive in order to detect amplitudes of reading signals, or placed in the transmitter of a communication device.
Please refer to FIG. 1, which is a diagram of a sample and hold circuit 100 according to the prior art. As shown in FIG. 1, the sample and hold circuit 100 comprises an operational amplifier 110, a plurality of switches S1, S2, S3, S4, S5, S6, S7, S8, and S9, a plurality of sampling capacitors Cs, and a plurality of feedback capacitors Cf. They are connected as shown in FIG. 1.
In a sample mode, the switches S1, S2, S5, S8, and S9 are turned on, and the switches S3, S4, S6, and S7 are turned off. Please refer to FIG. 2, which is a diagram of the sample and hold circuit 100 in the sample mode. At this time, an input signal is inputted into the two input ends of the sample and hold circuit 100. The input signal is then stored in the sampling capacitors Cs and the feedback capacitors Cf, where the two output ends are limited as differential zero because the switch S9 is turned on.
On the other hand, in a hold mode, the switches S1, S2, S5, S8, and S9 are turned off, and the switches S3, S4, S6, and S7 are turned on. Please refer to FIG. 3, which is a diagram of the sample and hold circuit 100 in the hold mode. As shown in FIG. 3, in the hold mode, the feedback capacitors form a negative feedback loop. As known by those skilled in the art, the charges stored in the sample mode are redistributed according to the capacitances of the sampling capacitors Cs and the feedback capacitors Cf. Assuming that the sampling capacitors Cs and the feedback capacitors Cf have the same capacitance, the two output ends output the signal sampled in the sample mode.
Please refer to FIG. 4, which is a signal diagram of the sample and hold circuit 100 shown in FIG. 1. As shown in FIG. 4, a clock ph1 and a clock ph2 are respectively utilized to define the sampling mode and the hold mode. In other words, the above-mentioned switches S1-S9 are turned on/off according to the clocks ph1 and ph2. Therefore, at the rising edge of the clock ph1, when ph1 is high and ph2 is low, the sample and hold circuit 100 samples the input signal and outputs a ground signal (this means that the signal is differential zero) for the switch S9 is turned on. On the other hand, at the rising edge of the clock ph2, when ph1 is low and ph2 is high, the sample and hold circuit 100 outputs the signal sampled in the sample mode.
Generally speaking, in order to provide a high resolution, meaning that to provide an output signal having a large bit number, the operational amplifier 110 is designed to have a high gain. In the sample mode, however, the switch S9 is utilized to limit the output of the operational amplifier 110 as a differential zero. Therefore, the switch S9 needs more time to charge/discharge when the gain of the operational amplifier 110 is very large.
In addition, if the charge/discharge time is more than half the period of the clock ph1, this represents that at the rising edge of the clock ph2, the output of the operational amplifier 110 is not back to differential zero. This result directly influences the circuit operation in the sample mode. In order to solve this problem, the switch S9 can be designed to have a bigger size such that the switch S9 can have a smaller turn-on resistor to reduce the charge/discharge time. This method also increases the chip area, however, and therefore raises costs because of this increased chip area.